Communication protocols have been in existence for some time, and govern the rules and requirements for the sending and receiving of information signal streams, generally comprising a plurality of bits, throughout a communication network. It is usual to undertake some degree of sampling of each bit of information of such a signal stream, to provide a determination of the logic state of the bit of the signal stream. The rate at which sampling is carried out is generally greater than the rate at which bits are transmitted and received. The bit sampling will therefore obtain multiple determinations of the logic state of any bit.
Bit sampling is carried out in the FlexRay communication protocol. The FlexRay communication protocol has been developed by a consortium of automotive manufacturers and semiconductor companies, to provide a distributed control and communication system for automotive applications. In the FlexRay communication protocol, it is required that a receiving node samples a received signal stream of bits, at a pre-determined bit sampling rate, which is greater than the rate at which the signal stream bits are being transmitted to the node. In one implementation, the bit sampling rate and the bit transmission rate are such that the sampling is carried out at eight sample points per bit of the signal stream. The sampling obtains a determination of the logic state of the signal stream bit received at each sample point.
In communication protocols it is known to provide processing of bit samples, to allow some degree of correction for errors in a signal stream.
In the FlexRay communication protocol, each receiving node stores a set of bit samples comprising the five most recently acquired samples of the signal stream. Each time a new sample is acquired, the stored set of samples is updated, and a majority voting operation is carried out on the updated set of samples. If a majority of any set of five most recently-acquired bit samples has a high logic state, then a voted value of the bit of the signal stream is determined to have a high logic state. If a majority of any set of five most recently-acquired bit samples has a low logic state, then a voted value of the bit of the signal stream is determined to have a low logic state. The voted values of the signal stream bits, generated by the majority voting operation on the bit samples, are strobed at a fifth sample point of each of a plurality of eight sample point cycles. The strobing comprises reading the voted value generated at that sample point, and this value is taken to be the logic state of the bit of the signal stream at that sample point and each subsequent sample point, until the voted values are next strobed.
Thus, in the FlexRay protocol, the received signal stream is firstly sampled, and a logic state of the signal stream obtained by the majority voting operation, and then the voted values are themselves sampled, or strobed, and the voted value at a particular sample point taken to be the logic state of the signal stream bits at this point and subsequent points until the voted values are next strobed. Using a majority voting operation on the bit samples, enables the received signal stream to be filtered, and allows some degree of correction of errors, such as glitches, in the received signal stream. However, this is counteracted to some degree by using a fixed strobe point for each cycle. It has been found that this present bit sampling implementation of the FlexRay protocol is not sufficiently robust against, inter alia, clock jitter, clock frequency inaccuracy, noise, and signal distortion, within a FlexRay network. This does not allow implementation of all topologies that the FlexRay communication protocol is intended to support. Improvements in signal error determination and correction are therefore being sought.
U.S. 20040179639 ‘Technique for over sampling to reduce jitter’, uses edge detection to determine bit values.
U.S. 20040091073 ‘Data recovery circuit, phase detection circuit and method for detecting and correcting phase conditions’, shifts the sampling clock to a ‘sweet spot’, according to a measured phase shift.
U.S. Pat. No. 5,948,116 ‘Bit error correction algorithm’, uses voting of redundant parallel sampling paths to determine bit values.
U.S. Pat. No. 3,614,623 ‘Adaptive system for correction of distortion of signals in transmission of digital data’, measures signal distortion based on an expected reception value, and feeds a correction value back to the transmitter.